Implementation of a kind of FPGA-based binary phase coded radar signal processor architecture

A flexible field programmable gate array based radar signal processor is presented. The radar signal processor mainly consists of five functional modules: radar system timer, binary phase coded pulse compression(PC), moving target detection(MTD), constant false alarm rate(CFAR) and target dots processing. Preliminary target dots information is obtained in PC, MTD, and CFAR modules and Nios II CPU is used for target dots combination and false sidelobe target removing. System on programmable chip(SOPC) technique is adopted in the system in which SDRAM is used to cache data. Finally, a FPGA-based binary phase coded radar signal processor is realized and simulation result is given.